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TMS320C5515
www.ti.com
SPRS645F – AUGUST 2010 – REVISED OCTOBER 2013
5.8
5.8.1
Wake-up Events, Interrupts, and XF
The device has a number of interrupts to service the needs of its peripherals. The interrupts can be
selectively enabled or disabled.
Interrupts Electrical Data/Timing
Table 5-7. Timing Requirements for Interrupts (1) (see Figure 5-13 )
CV DD = 1.05 V
NO.
CV DD = 1.3 V
MIN
MAX
UNIT
1
2
t w(INTH)
t w(INTL)
Pulse duration, interrupt high CPU active
Pulse duration, interrupt low CPU active
2P
2P
ns
ns
(1)
P = 1/SYSCLK clock frequency in ns. For example, when the CPU core is clocked at 100 MHz, use P = 10 ns. For example, when the
CPU core is clocked att 120 MHz, use P = 8.3 ns.
1
INTx
2
Figure 5-13. External Interrupt Timings
5.8.2
Wake-Up From IDLE Electrical Data/Timing
Table 5-8. Timing Requirements for Wake-Up From IDLE (see Figure 5-14 )
CV DD = 1.05 V
NO.
CV DD = 1.3 V
MIN
MAX
UNIT
1
t w(WKPL)
Pulse duration, WAKEUP or INTx low, SYSCLKDIS = 1
30.5
μs
Table 5-9. Switching Characteristics Over Recommended Operating Conditions For Wake-Up From
IDLE (1) (2) (3) (4) (see Figure 5-14 )
CV DD = 1.05 V
NO.
PARAMETER
CV DD = 1.3 V
MIN
TYP
MAX
UNIT
IDLE3 Mode with SYSCLKDIS = 1,
WAKEUP or INTx event, CLK_SEL =
1
D
ns
2
t d(WKEVTH-C
KLGEN)
Delay time, WAKEUP pulse complete to
CPU active
IDLE3 Mode with SYSCLKDIS = 1,
WAKEUP or INTx event, CLK_SEL =
C
ns
0
IDLE2 Mode; INTx event
3P
ns
(1)
(2)
(3)
(4)
D = 1/ External Clock Frequency (CLKIN).
C = 1/RTCCLK= 30.5 μ s. RTCCLK is the clock output of the 32.768-kHz RTC oscillator.
P = 1/SYSCLK clock frequency in ns. For example, when the CPU core is clocked at 100 MHz, use P = 10 ns.
Assumes the internal LDOs are used with a 0.1uF bandgap capacitor.
Copyright ? 2010–2013, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
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